Drovia

Research Methodology

Machine Learning–Assisted Pathway for IR-Drop Aware Timing Optimization in Advanced CMOS Technologies

ML Architecture

Drovia employs a dual machine learning approach for timing optimization:

  • SVMSupport Vector Machine with linear kernel for efficient binary classification
  • RFRandom Forest for handling non-linear relationships and feature importance
  • FEATUREExtraction of resistance, capacitance, timing, voltage, and current parameters
  • OPTIMIZEStrategic timing optimization between aggressor and victim gates
Research Process

Our research follows a structured approach to IR-drop aware timing optimization:

  1. Circuit simulation using HSPICE with aggressor-victim characterization
  2. Parameter randomization (supply voltage, resistance, capacitance)
  3. Feature extraction and data preprocessing
  4. ML model training (SVM and Random Forest)
  5. Performance evaluation across 1-5% thresholds
  6. Timing optimization analysis and validation
  7. ECO integration methodology development
  8. Publication and tool integration preparation

Research Focus Areas

Drovia addresses three critical VLSI design challenges

IR Drop Mitigation

Optimizing timing relationships to minimize IR drop impact on critical paths, achieving less than 1% delay impact while maintaining circuit performance.

Crosstalk Reduction

Strategic timing optimization between aggressor and victim gates to reduce crosstalk effects and improve signal integrity in advanced CMOS technologies.

Timing Closure

Machine learning-assisted approach to improve timing closure efficiency, reducing design iterations and enabling automated optimization workflows.

Expected Outcomes

By the conclusion of this research initiative, we expect to deliver:

95% Classification Accuracy

ML models achieving high accuracy in identifying critical aggressors for timing optimization

<1% Critical Path Impact

Minimal performance degradation while effectively mitigating IR-drop and crosstalk effects

ECO Integration Ready

Methodology designed for seamless integration with PrimeTime ECO for automated optimization

Publication & Tool Integration

Research paper and practical implementation for commercial VLSI design workflows